In the field of a high voltage withstanding semiconductor device that controls a voltage exceeding several hundred volts, element characteristics wherein heat emission, that is to say, loss is suppressed are required because the current handled is great. In addition, as for a driving system of a gate that controls this voltage and current, a voltage drive element of which the driving circuit is small so that the loss therein is small is desirable.
In recent years, because of the above described reasons, an insulated gate bipolar transistor, that is to say, an IGBT, has come into wide use as an element wherein a voltage drive is possible and loss is small in this field. The structure of this IGBT is a structure wherein the impurity concentration of the drain is lowered so as to secure the withstanding voltage in a MOS (metal oxide semiconductor) transistor and the drain can be regarded as a diode in order to reduce the drain resistance.
Thus, a diode carries out a bipolar operation in an IGBT and, therefore, in the present application the source of the MOS transistor of an IGBT is referred to as an emitter and the drain is referred to as a collector.
A voltage of several hundred volts is applied between the collector and the emitter of an IGBT, which is a voltage drive element and which is controlled by the gate voltage of which the voltage is ±several volts to several tens of volts. In addition, in many cases an IGBT is used as an inverter, wherein the voltage between the collector and the emitter is low in the case that the gate is in the on condition so that a great amount of current flows while no current flows and the voltage between collector and the emitter is high in the case that the gate is in the off condition.
Since the operation of an IGBT is carried out conventionally in the above described mode, the loss is divided into constant loss, which is a product of current and voltage in the on condition, and switching loss at the time of transition wherein the on condition and the off condition are switched. The product of leak current and voltage in the off condition is so small that it can be ignored.
On the other hand, it is important to prevent breakdown of the element during an abnormal state such as, for example, in the case that the load is short circuited. In this case, the gate is turned on while the power source voltage of several hundred volts is applied between the collector and the emitter so that a large current flows.
In an IGBT having a structure wherein a MOS transistor and a diode are connected in series the maximum current is controlled by the saturation current of the MOS transistor. Therefore, the current control works even at the time of short circuiting, as described above, so that breakdown of the element due to heat emission of a constant period of time can be prevented.
FIG. 75 is a cross sectional view schematically showing the configuration of a semiconductor device according to a prior art. An IGBT is formed in a semiconductor substrate having a first main surface and a second main surface that are opposed to each other. A p-type body region 102 is formed on the first main surface side of an n− silicon layer 101 and an n-type emitter region 103 and a p+ impurity diffusion region 106 are formed in the first main surface within this p-type body region 102.
A trench 101a for a gate is created so as to penetrate this n-type emitter region 103 and this p-type body region 102 and so as to reach to n− silicon layer 101. A gate insulating film 104a is formed so as to extend along the inner surface of this trench 101a for a gate and a gate electrode 105a is formed so as to fill in trench 101a for a gate. An insulating film 122A made of an oxide film is formed on the upper surface of gate electrode 105a. 
This n− silicon layer 101, n-type emitter region 103 and gate electrode 105a form an insulating gate type field effect transistor (here MOS transistor) having n− silicon layer 101 as a drain and having n-type emitter region 103 as a source.
Insulating films 109 and 122B are formed above the first main surface and a contact hole 109a is created in these insulating films 109 and 122B so as to reach to the surface of n-type emitter region 103 and p+ impurity diffusion region 106. A barrier metal layer 110 is formed on the upper surfaces of insulating films 109 and 122B as well as on the inner surface of contact hole 109a and a silicide layer 121a is formed in a contact portion between barrier metal layer 110 and the semiconductor substrate. An emitter electrode 111 is formed above the first main surface so as to be electrically connected to n-type emitter region 103 and to p+ impurity diffusion region 106 via this barrier metal layer 110 and this silicide layer 121a. 
An n-type buffer region 107 and a p-type collector region 108 are formed on the second main surface side of n− silicon layer 101. A collector electrode 112 made of, for example, an aluminum compound is electrically connected to this p-type collector region 108.
In such a semiconductor device according to the prior art, thickness t2 of the semiconductor substrate is 300 μm to 400 μm and, in some cases, is 500 μm.
Next, a manufacturing method for the semiconductor device according to the prior art shown in FIG. 75 is described.
FIGS. 76 to 85 are schematic cross sectional views showing the steps, in order, of the manufacturing method for the semiconductor device according to the prior art. In reference to FIG. 76, first n-type buffer region 107 and n− silicon layer 101 are formed above p-type semiconductor substrate 108 that becomes the collector region through an epitaxial growth method. p-type body region 102 is formed on the first main surface side of this n− silicon layer 101 and insulating film 131 made of, for example, a silicon oxide film is formed on top of that.
In reference to FIG. 77, this insulating film 131 is patterned by means of conventional photomechanical technology and etching technology. This patterned insulating film 131 is used as a mask so that ion implantation, or the like, is carried out on p-type body region 102 and, thereby, n-type emitter region 103 is formed. After this, insulating film 131 is removed.
In reference to FIG. 78, a thermal oxide film 132 and a CVD (chemical vapor deposition) oxide film 133 are sequentially formed over the entirety of the first main surface and, after that, patterning is carried out. This patterned thermal oxide film 132 and CVD oxide film 133 are used as a mask so as to carry out anisotropic etching on the semiconductor substrate. Thereby, trench 101a for a gate is created so as to penetrate n-type emitter region 103 and p-type body region 102 and so as to reach to n− silicon layer 101.
In reference to FIG. 79, processes such as isotropic plasma etching and sacrificial oxidation are carried out. Thereby, the opening and the bottom portion of trench 101a for a gate become rounded and unevenness of the sidewalls of trench 101a for a gate is made flat. Furthermore, a sacrificial oxide film 132a is formed so as to extend the inner surface of trench 101a for a gate and is integrated into thermal oxide film 102. After this, CVD oxide film 133, thermal oxide film 132 and sacrificial oxide film 132a are removed.
In reference to FIG. 80, the surface of the semiconductor substrate is exposed as a result of this removal.
In reference to FIG. 81, gate insulating film 104a made of a silicon oxide film, or the like, is formed on the inner surface of trench 101a for a gate and on the first main surface of the semiconductor substrate. Furthermore, a conductive layer 105 made of a polycrystal silicon, or the like, to which phosphorus is introduced so as to have a high concentration is formed in the first main surface of the semiconductor substrate so as to fill in trench 101a for a gate. After this, this conductive layer 105 is removed until the upper surface of gate insulating film 104a is exposed.
In reference to FIG. 82, thereby, conductive layer 105 is allowed to remain so as to fill in trench 101a for a gate so that gate electrode 105a is formed. After this, insulating film 122A is formed on the upper surface of gate electrode 105a. 
In reference to FIG. 83, an insulating film 109 made of, for example, a silicate glass and an insulating film 122B made of a CVD oxide film are sequentially formed and, after that, are patterned so as to open contact hole 109a. 
In reference to FIG. 84, barrier metal layer 110 is formed over the entirety of the surface. After this, lamp annealing, or the like, is carried out and, thereby, silicide layer 121a is formed in a contact portion between barrier metal layer 110 and the semiconductor substrate. Emitter electrode 111 is formed on barrier metal layer 110.
In reference to FIG. 85, p-type collector region 108 is removed through polishing.
After this, collector electrode 112 is formed so as to be connected to p-type collector region 108 in the second main surface and the semiconductor device according to the prior art, shown in FIG. 75, is completed.
In the configuration shown in FIG. 75, p-type collector region 108 of a high concentration, which is thick, exists on the second main surface side of semiconductor substrate and, therefore, the injection efficiency of holes from the collector side (second main surface side) becomes high at the time when the device turns ON. Thereby, the lowering of the ON voltage (lowering of RON) can be implemented.
In the configuration shown in FIG. 75, however, a main current that flows when the device turns ON becomes very large and the saturation current becomes large and, as a result, the device itself cannot control the current and it is difficult to secure or increase the withstanding capacity against breakdown at the time of device operation with no load.
In addition, in the configuration shown in FIG. 75, p-type collector region 108 of a high concentration, which is thick, exists on the second main surface side and, therefore, the injection efficiency of holes from the collector side (second main surface side) at the ON time of the device becomes very high. Therefore, the switching loss increases at the time of turning off in the case that the voltage Vce between the collector and the emitter is high (in the case of switching at high voltage).
Furthermore, in the manufacturing method shown in FIGS. 76 to 85, p-type collector region 108 and n-type buffer region 107 exist on the second main surface side from the beginning of the process and n-type buffer region 107 and n− silicon layer 101 are formed through epitaxial growth. Therefore, the substrate tends to become costly and freedom in thickness of the substrate is limited.